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8533agi-01 1 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer b lock d iagram p in a ssignment ICS8533I-01 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view v ee clk_en clk_sel clk nclk pclk npclk nc nc v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q0 nq0 v cc q1 nq1 q2 nq2 v cc q3 nq3 clk nclk pclk npclk q0 nq0 q1 nq1 q2 nq2 q3 nq3 0 1 clk_en clk_sel d q le g eneral d escription the ICS8533I-01 is a low skew, high perfor- mance 1-to-4 differential-to-3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ICS8533I-01 has two selectable clock inputs. the clk, nclk pair can accept most standard dif- ferential input levels. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels. the clock enable is internally synchronized to eliminate runt pulses on the out- puts during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ICS8533I-01 ideal for those applications demand- ing well defined performance and repeatability. f eatures ? four differential 3.3v lvpecl outputs ? selectable differential clk, nclk or lvpecl clock inputs ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? pclk, npclk supports the following input types: lvpecl, cml, sstl ? maximum output frequency: 650mhz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclk input ? output skew: 30ps (maximum) ? part-to-part skew: 150ps (maximum) ? propagation delay: 1.5ns (maximum), clk/nclk ? additive phase jitter, rms: 0.060ps (typical) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs5) and lead-free (rohs 6) packages hiperclocks? ic s
8533agi-01 2 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 1v e e r e w o p. n i p y l p p u s e v i t a g e n 2n e _ k l ct u p n ip u l l u p . t u p n i k c o l c w o l l o f s t u p t u o k c o l c , h g i h n e h w . e l b a n e k c o l c g n i z i n o r h c n y s . h g i h d e c r o f e r a s t u p t u o q n , w o l d e c r o f e r a s t u p t u o q , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3l e s _ k l ct u p n in w o d l l u p . s t u p n i k l c p n , k l c p l a i t n e r e f f i d s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i k l c n , k l c s t c e l e s , w o l n e h w 4k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 6k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 7k l c p nt u p n ip u l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 9 , 8c nd e s u n u. t c e n n o c o n 8 1 , 3 1 , 0 1v c c r e w o p. s n i p y l p p u s e v i t i s o p 2 1 , 1 13 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 12 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
8533agi-01 3 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l c p r o k l ck l c p n r o k l c n3 q : 0 q3 q n : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n f igure 1. clk_en t iming d iagram nclk, npclk clk, pclk clk_en nq0:nq3 q0:q3 enabled disabled s t u p n is t u p t u o n e _ k l cl e s _ k l ce c r u o s d e t c e l e s3 q : 0 q3 q n : 0 q n 00 k l c n , k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 01 k l c p n , k l c pw o l ; d e l b a s i dh g i h ; d e l b a s i d 10 k l c n , k l cd e l b a n ed e l b a n e 11 k l c p n , k l c pd e l b a n ed e l b a n e e g d e k c o l c t u p n i g n i l l a f d n a g n i s i r a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c r e t f a k l c p n , k l c p d n a k l c n , k l c e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n i . 1 e r u g i f n i n w o h s s a d e b i r c s e d s a s t u p n i . b 3 e l b a t n i
8533agi-01 4 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 2 5a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i n e _ k l cv n i v = c c v 5 6 4 . 3 =5a l e s _ k l cv n i v = c c v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i n e _ k l cv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a l e s _ k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv c c v = n i v 5 6 4 . 3 =5a k l cv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v v s i k l c n d n a k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. func- tional operation of product at these conditions or any condi- tions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect prod- uct reliability.
8533agi-01 5 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t able 4d. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c t able 5. ac c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c pv c c v = n i v 5 6 4 . 3 =0 5 1a k l c p nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l c pv c c v , v 5 6 4 . 3 = n i v 0 =5 -a k l c p nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 01v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 1 +v c c v v h o 3 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 3 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c p n d n a k l c p r o f e g a t l o v t u p n i m u m i x a m e h t s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + 0 5 h t i w d e t a n i m r e t s t u p t u o : 3 e t o n v o t c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 6z h m t d p ; y a l e d n o i t a g a p o r p 1 e t o n k l c n , k l c5 1 . 15 . 1s n k l c p n , k l c p0 . 13 . 1s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 3s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 1s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 0 6 0 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o 0 0 30 0 8s p c d oe l c y c y t u d t u p t u o 7 43 5% f t a d e r u s a e m s r e t e m a r a p l l a . e s i w r e h t o d e t o n s s e l n u z h m 0 5 6 . r e t t i j d d a t o n s e o d t r a p e h t . t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c o t e l c y c e h t . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
8533agi-01 6 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer a dditive p hase j itter input/output additive phase jitter at 156.25mhz = 0.060ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 - 160 -170 -180 - 190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the fun- damental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power as with most timing specifications, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired ap- plication over the entire time record of the signal. it is math- ematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
8533agi-01 7 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer p arameter m easurement i nformation 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel p ropagation d elay o utput s kew o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod v cmr cross points v pp v ee npclk, nclk v cc pclk, clk scope qx nqx lvpecl 2v -1.3v 0.165 t sk(o) nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v sw i n g t pd npclk, nclk q0:q3 nq0:nq3 pclk, clk v cc v ee t pw t period t pw t period odc = x 100% q0:q3 nq0:nq3
8533agi-01 8 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput r2 1k v cc clk_in + - r1 1k c1 0.1uf v_ref figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the w iring the d ifferential i nput to a ccept s ingle e nded l evels ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
8533agi-01 9 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces sug- f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river gested here are examples only. please consult with the vendor of the driver component to confirm the driver termination re- quirements. for example in figure 3a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8533agi-01 10 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4f show inter- face examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces sug- gested here are examples only. if the driver is from another vendor, use their termination recommendation. please con- sult with the vendor of the driver component to confirm the driver termination requirements. f igure 4a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 4b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 4c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 4f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hipercloc ks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 4e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hipercloc ks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 4d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
8533agi-01 11 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and mini- mize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process varia- tions. f igure 5b. lvpecl o utput t ermination f igure 5a. lvpecl o utput t ermination v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin t ermination for lvpecl o utputs
8533agi-01 12 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS8533I-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8533I-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 52ma = 180.2mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 180.2mw + 120mw = 300.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.300w * 66.6c/w = 105c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 6. t hermal r esistance ja for 20- pin tssop, f orced c onvection 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8533agi-01 13 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
8533agi-01 14 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ICS8533I-01 is: 404 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8533agi-01 15 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, ms-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
8533agi-01 16 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - i g a 3 3 5 8 s c i1 0 i g a 3 3 5 8 s c ip o s s t d a e l 0 2e b u tc 5 8 o t c 0 4 - t 1 0 - i g a 3 3 5 8 s c i1 0 i g a 3 3 5 8 s c ip o s s t d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 1 0 - i g a 3 3 5 8 s c il 1 0 i a 3 3 5 8p o s s t " e e r f d a e l " d a e l 0 2e b u tc 5 8 o t c 0 4 - t f l 1 0 - i g a 3 3 5 8 s c il 1 0 i a 3 3 5 8p o s s t " e e r f d a e l " d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in lif e support devices or critical medical instruments.
8533agi-01 17 rev. a december 6, 2007 ICS8533I-01 l ow s kew , 1- to -4 d ifferential - to -3.3v lvpecl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 9 t 1 8 0 1 6 1 . e t o n e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d e t a d p u . e c a f r e t n i t u p n i k c o l c l c e p v l . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 1 2 / 4 a 9 t6 1g n i k r a m e e r f d a e l n o n d e g n a h c - e l b a t n o i t a m r o f n i g n i r e d r o 7 0 - 6 - 2 1

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